Design of thyristor ESD protection structure with low trigger voltage
Abstract: In the current integrated circuit design, a large number of thyristor design structures are used for ESD protection, but the general SCR protection structure is difficult to meet the current low voltage and some special requirements for integrated circuit ESD protection. A thyristor-structured protection circuit with a low trigger voltage was studied. The combination of parasitic parameters and process parameters satisfied the design requirements for low trigger voltage.
Keywords: integrated circuit design; electrostatic protection; thyristor structure; trigger current
1 Introduction
Electrostatic discharge (ESD) poses a great threat to the reliability of CMOS integrated circuits [1]. With the improvement of the design level of integrated circuits and the expansion of application fields, for CMOS integrated circuits, due to the smaller feature size and lower power supply voltage, ESD protection can no longer meet the requirements using only traditional diode structures. In the currently widely used ESD protection circuit, the SCR structure has the highest ESD protection performance per unit area [2], and it also has good high-current characteristics [3]. As shown in Figure 1, it is a schematic diagram of a common SCR structure.
There are adjacent N-wells and P-wells on P-type substrates, P-type implanted regions in P-wells, N-type implanted regions in P-wells, P-type implanted regions in N-wells, and N-type implants in N-wells. The area constitutes a PNPN semiconductor structure.
Figure 2 is an equivalent circuit diagram of the SCR protection structure shown in Figure 1. Its structure consists of a parasitic PNP Transistor Q1, a parasitic NPN transistor Q2, and parasitic resistances R1, R2.
The trigger voltage of the SCR protection structure shown in Figure 1 is the avalanche breakdown voltage of the PN junction formed by the P-well and N-well. In general, the doping concentration of the P-well and N-well is low, and the trigger voltage is usually greater than tens of volts. In this case, it is possible that the SCR protection structure has not been turned on, and the internal circuit of the CMOS integrated circuit is damaged due to ESD discharge.
In order to reduce the trigger voltage of SCR protection structure and meet the requirement of large trigger current in circuit applications, an improved SCR protection structure is designed in this paper, which can effectively solve the above problems.
2 Design of SCR structure with high trigger current and low turn-on voltage
LVTSCR design principles. For the low-voltage triggered SCR (LVTSCR) design structure, from the ESD discharge principle [4], mainly consider the positive ESD pulse (ie I/O PAD is positive potential, GND is At zero potential, an avalanche breakdown occurs in the NMOS transistor consisting of an N-type implanted region, a P-well, and an N-type implanted region in the device, and the parasitic PNP transistor and the parasitic NPN transistor turn on and discharge the ESD current. In the reverse ESD pulse (ie I/O PAD is negative, GND is zero), the entire LVTSCR device exhibits a positive bias diode characteristic. Since the trigger voltage of the LVTSCR is the avalanche breakdown voltage of the NMOS transistor in the device, the trigger voltage of the LVTSCR protection structure is much smaller than the SCR protection structure shown in Fig. 1 [5].
However, practical applications show that the majority of the failure parts of SCR devices are on the NMOS tube where avalanche breakdown occurs. Although the NMOS transistor lowers the trigger voltage of the entire SCR protection structure, its ESD level limits the ESD protection level of the SCR protection structure.
According to the above design principles, the SCR ESD protection device with low trigger voltage proposed in this paper can fully exert the high current characteristics and protection capability of the SCR structure and provide a high level of ESD protection. The specific structure is shown in the figure. 3.
The thyristor structure proposed herein includes a P-type substrate on which an N-well and P-well region are formed by implantation. An N-type implanted region and a P-type implanted region are formed by implantation in the N-well region. The N-type implanted region and the P-type implanted region are connected to the first input I/O PAD of the device. The P-well region includes an N-type implanted region and a P-type implanted region. The surface between the two N-type implanted regions has a gate oxide layer, and the surface of the gate oxide layer is a gate formed by polysilicon deposition. The N-type implanted region is connected to the first input I/O PAD of the device through a resistor, the N-type implanted region, the P-type implanted region and the polysilicon gate are connected to the second input GND of the device.
Compared with the existing SCR structure, in the electrostatic discharge protection structure proposed in this paper, the N-type implanted region in the P well and the first input I/O PAD of the device are connected through a resistor, and the NMOS transistor in FIG. 3 is leaked. The pole is connected to the first input I/O PAD through the N-well. The majority of failures in existing SCR structures are on NMOS tubes where avalanche breakdown occurs. Since the positive ESD is discharged (that is, I/O PAD is positive, GND is zero potential), in addition to the aforementioned PNPN current drain path, the N-type implant region, P-well, and N-type implant region below the NMOS transistor The resulting parasitic NPN triode is also the ESD current drain path. In general, the current drain capability of an NPN tube is not as good as that of a PNPN structure. Therefore, the above-mentioned NMOS tube is the first to be damaged.
The difference between the electrostatic discharge protection structure proposed in this paper and the existing SCR is that the drain of the NMOS transistor and the first input I/O PAD are connected through a resistor. By appropriately selecting the resistance of this resistor, the flow through the NMOS can be restricted. The parasitic NPN transistor current under the tube prevents this transistor from being damaged during ESD discharge. The resistance of the resistor cannot be chosen too large, otherwise the above-mentioned PNPN structure is not enough to be triggered to conduct. Under this condition, the SCR electrostatic discharge protection device proposed in this paper is completely determined by the PNPN structure. Therefore, it can give full play to the large current characteristics and protection capability of the SCR structure and provide a high level of ESD protection.
3 Actual circuit application of SCR structure
Based on the above design considerations, the above-described LVTSCR structure is used in a plurality of actual circuits, and a very good protective effect is obtained. The specific circuit description is as follows.
3.1 SCR Structure of General Input
For the input, the structure of PMOS and diodes is added to ensure that the input is protected against external positive and negative ESD pulses (Figure 4).
3.2 General Output SCR Structure
For the protection of the output, from the experimental results, only using the structure of PMOS + SCR can also achieve very good protection (Figure 5).
3.3 SCR Structure of I2C I/O Port
For the I2C I/O structure, a large trigger current is required to satisfy the function of the circuit. The above structure can well meet the design requirements [6].
With the SCR protection structure of the above structure, the ESD protection capability of 4 kV can be achieved, and the device's ability to prevent LATCHUP is also greatly improved. The application of the device as an industrial-grade ESD level can be satisfied (Figure 6).
4 Conclusion
The design of the SCR structure is complex. Device technology, layout design, and specific circuitry all affect the actual level of ESD. The design ideas in this paper can be applied to other SCR designs, and the level of ESD can also be improved [7].
